The present invention relates to switching state retention circuits of the kind permitting a switching state at the input thereof to appear at the output thereof only after an enabling signal has permitted such a result and, more particularly, such switching state retention circuits which are formed by use of a feedback loop path arrangement.
There are many uses in digital systems for D-type flip-flops, i.e. data latches. Such latches are used frequently to store a signal value representing data received at a data input for a duration of time after an enabling signal of a particular logic value has also been received at an enable input. This is useful, for instance, in permitting subsequent portions of the digital system to operate on a fixed value signal at the output of the latch even though further changes are occurring at the latch data input.
For the representation shown in FIG. 1 of such a D-type flip-flop, 10, the typical operating arrangement has the enable input, 11, at the "1" logic value if the signal values occurring on the data input, 12, are (i) to be presented at the latch output, 13, as they occur at input 12, but (ii) to not be stored and presented as stored at the latch output 13 despite logic state changes subsequently occurring at input 12. Alternatively, the "0" logic value is provided at enable input 11 if a logic signal on data input 12 is to be stored and a representation thereof presented at output 13, with output 13 thereafter remaining fixed at this logic state value occurring at data input 12 just before the logic value at enable input 11 went to this "0" logic state.
A common way of implementing the D-type latch of FIG. 1 is shown in the logic symbol system diagram of FIG. 2A, particularly if implemented in complementary metal-oxide-semiconductor (CMOS) technology, i.e. based on using p-channel and n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) pairs as the active components in the circuit. The same designation numerals are used in FIG. 2A for the inputs and outputs there as are used for the corresponding inputs and outputs in FIG. 1.
Data input 12 in FIG. 2A is connected to the input of a controlled data propagation inverter, 14. Inverter 14 is controlled by enabling signals applied to input 11, as in FIG. 1, and to a further input, 11'. The signal at input 11' is just the logical complement of that at input 11 and so can be provided by merely connecting an inverter between input 11 and input 11' to exactly duplicate the situation of FIG. 1. However, for clarity purposes, two separate inputs are shown in FIG. 2A. The logic signal to be provided at input 11 will be designated as the ENABLE signal while that to be provided at input 11' will be designated as the ENABLE' as the logical complement signal.
If the ENABLE signal at input 11 takes a logical "1" value, so that complementary signal ENABLE'has a logical "0" value, whatever logic state value appears at data input 12 will appear inverted, i.e. the opposite state, at a circuit node, 15, to which the output of controlled inverter 14 is connected, at least after the propagation delay through inverter 14. If, on the other hand, the logic state values are reversed at inputs 11 and 11', from those just described, any changes in logic states subsequently occurring at data input 12 will have no further effect on the logic state present at the output of controlled inverter 14, and so at circuit node 15, until yet another such logic state reversal. That is, the output of inverter 14 is isolated from logic state changes on data input 12 in this latter situation.
Also connected to node 15 is the input of a further inverter, 16. The output of inverter 16 is connected to the input of yet another inverter, 17. Inverters 16 and 17 are ordinary logic inverters. If they are each electrically energized, the output of each will be at a logic state value opposite that appearing at the input thereof.
The output of inverter 17 is connected to the input of a transmission gate, 18. The output of transmission gate 18 is, in turn, connected to circuit node 15 to thereby form a feedback path arrangement, or feedback loop, from node 15 through inverters 16 and 17, through transmission gate 18, and back to node 15.
Transmission gate 18 can be directed by the ENABLE and the ENABLE' signals to provide a low impedance, i.e. high conductivity, electrical circuit path between the input and the output of this transmission gate. This occurs when the signal ENABLE at input 11 is in the "0" logic state and the signal ENABLE' at input 11' is in the "1" logic state. Alternatively, these signals can direct transmission gate 18 to have a high impedance, i.e. low conductivity, electrical circuit path between the input and the output thereof. This occurs when the logic state values at inputs 11 and 11' are the reverse of those described for the high conductivity situation. Thus, transmission gate 18 provides a highly conductive circuit path (acting as a closed switch) substantially only if the logic state on the output of controlled inverter 14 is independent of the signal occurring at data input 12, but provides a low conductivity path (acting as an open switch) substantially only if the logic state values on the output of controlled inverter 14 follow those occurring on data input 12.
Finally, node 15 in the circuit of FIG. 2A has the input of a further ordinary inverter, 19, connected thereto. The output of inverter 19 is in turn connected to latch output 13.
In operation, the provision of a logic "1" for the ENABLE signal at input 11 and a logic "0" for the ENABLE' signal at input 11' leads to the logic state values occurring at latch data input 12 being provided to inverted circuit node 15 at the output of controlled inverter 14 after the propagation delay through inverter 14. Such logic state values provided at circuit node 15 will result in the opposite logic state values occurring at the output of inverter 16, and so at the input of inverter 17. Inverter 17 will invert these logic state values again as they appear at its output.
Thus, the same logic state values that occur at circuit node 15 will also occur at the output of inverter 17 after propagation through inverters 16 and 17 which are opposite to those occurring on data latch data input 12. The time a logic state change on data input 12 takes to propagate to the output of inverter 17 is the "setup time." However, the logic states at the output of inverter 17 will have no effect on circuit node 15 as transmission gate 18, for these values of the signals ENABLE and ENABLE', will be in a low conductivity state. This prevents the logic state values occurring at the output of inverter 17 from affecting circuit node 15 in any significant way since there is, in effect, no circuit path from the output of inverter 17 to circuit node 15.
Because of the inversion action of inverter 19, logic state values appearing at circuit node 15 will lead to the opposite logic state appearing at the output of inverter 19, and so at latch output 13. Thus, the logic state occurring on latch output 13 will be just that occurring on data input 12 after the propagation delays through controlled inverter 14 and inverter 19.
Alternatively, if the logic values for the ENABLE signal and the ENABLE' logic signal reverse so that ENABLE has a "0" value and ENABLE' has a "1" value, the logic state occurring on circuit node 15 after this reversal will no longer be affected by the logic states occurring at data input 12 but, at least initially, will be an inverted version of that which was present on data input 12 at the time of such logic state value reversal in the enabling signals. This logic state value is initially maintained at the output of inverter 14, and at circuit node 15, at least temporarily because of the charging of the parasitic capacitances associated with circuit node 15. This reversal of the logic state values of the enabling signals also switches transmission gate 18 into the high conductivity state (during the "hold time" between this reversal and the output of inverter 14 becoming isolated from its input) so that the logic state occurring at the output of inverter 17 is now applied to circuit node 15. The "hold time" must elapse after a logic state change occurs on terminal 12 to be certain that the inverted logic state is established on node 15. As described just above, the logic state value occurring at the output of inverter 17 is just that occurring at circuit node 15 so that they are consistent with one another (if the "setup time" has elapsed which is the time between a logic state change occurring on terminal 12 until the logic state change is propagated through to the output of inverter 17, and this time must elapse after a logic state change occurs on terminal 12 before an isolation of the output of inverter 14 occurs if the logic state on terminal 12 is to be stored certainly). This common logic state on node 15 and at the output of inverter 17 is maintained because of the one reinforcing the other due to the feedback path arrangements through inverters 16 and 17 and transmission gate 18.
The actual CMOS technology implementation of the logic symbol system of FIG. 2A is shown in FIG. 2B. Controlled inverter 14 is formed of first and second p-channel MOSFET's, 20 and 21. The source of transistor 20 is electrically connected to a terminal means, 22, adapted for connection to a source of positive voltage.
The drain of transistor 20 is electrically connected to the source of transistor 21. The drain of transistor 21 is electrically connected to one of two n-channel MOSFET's, 23 and 24, which are also part of controlled inverter 14. The drain of transistor 21 is electrically connected to the drain of transistor 23 to form the output of controlled inverter 14. The source of transistor 23 is electrically connected to the drain of transistor 24. The source of transistor 24 is electrically connected to a terminal means, 25, adapted for connection to the ground reference voltage.
The gates of transistors 20 and 24 are electrically connected together, to form the input of controlled inverter 14, and to data latch data input terminal 12. The gate of transistor 21 is electrically connected to input 11' at which the signal ENABLE' is provided. The gate of transistor 23 is electrically connected to input 11 at which the signal ENABLE is provided. Thus, p-channel MOSFET 21 and n-channel MOSFET 23 together serve to either (i) isolate, through being switched to the "off" condition, the output of controlled inverter 14, connected to circuit node 15, from electrical changes occurring in p-channel MOSFET 20 and n-channel MOSFET 24 as a result of being controlled by logic signals at latch data input 12, or (ii) to connect, through being switched to the "on" condition, the drains of MOSFET's 20 and 24 to the output of controlled inverter 14 and so to circuit node 15.
Inverter 16 is shown formed with a p-channel MOSFET, 26, and a n-channel MOSFET 27. The source of transistor 26 is electrically connected to terminal means 22 while the source of transistor 27 is electrically connected to terminal means 25. The drains of transistors 26 and 27 are electrically connected together to form the output of inverter 16, as are the gates of these two transistors, to form the input of inverter 16, which gates in turn are electrically connected to circuit node 15.
Inverter 17 is similarly shown in FIG. 2B formed of a p-channel MOSFET, 28, and a n-channel MOSFET, 29. The source of transistor 28 is electrically connected to terminal means 22 and the source of transistor 29 is electrically connected to terminal means 25. The drains of transistors 28 and 29 are electrically connected together to form the output of inverter 17, and so are the gates of these transistors, to form the input of inverter 17, these gates also being electrically connected to the common drains of transistors 26 and 27 forming the output of inverter 16.
Transmission gate 18 is shown in FIG. 2B formed of a p-channel MOSFET, 30, and a n-channel MOSFET, 31. The lower terminating regions in that figure of each of MOSFET's 30 and 31, serving as source and drain, are electrically connected to one another and to the common drain regions of transistors 28 and 29 forming the output of inverter 17. The upper terminating regions in FIG. 2B of MOSFET's 30 and 31, also serving as a source and drain, are electrically connected to one another and to circuit node 15.
Finally, inverter 19 is formed of a p-channel MOSFET, 32, and a n-channel MOSFET, 33. The source of transistor 32 is electrically connected to terminal means 22 and the source of transistor 33 is electrically connected to terminal means 25. The drains of transistors 32 and 33 are electrically connected to one another, to form the output of inverter 19, and to latch output 13. The gates of transistors 32 and 33 are electrically connected to one another, to form the input of inverter 19, and to circuit node 15. The substrates of all of the MOSFET's shown in FIG. 2B have the usual electrical connections even though, to maintain clarity, they are not explicitly shown in that figure: the substrates of all the p-channel MOSFET's are electrically connected to terminal means 22 while the substrates of all of the n-channel MOSFET's are electrically connected to terminal means 25.
Inverters 16, 17 and 19, and the inverter formed by MOSFET's 20 and 24 considered together as part of controlled inverter 14 (with MOSFET's 21 and 23 in the "on" condition), operate in a conventional manner for logic inverters. That is, a low voltage logic state at the common drain output (separated by MOSFET's 21 and 23 in the case of inverter 14) for each inverter results from a high voltage logic state occurring on the common gate input thereof. This occurs through the n-channel transistor in each being in the "on" condition and the p-channel transistor in each being in the "off" condition. Conversely, a high voltage logic state at the common drain output for each, as the result of a low voltage logic state at the common gate input of each results from the n-channel transistor in each inverter being in the "off" condition and the p-channel transistor in each being in the "on" condition.
Transmission gate 18 is in the high conductivity transmission condition, between the two commonly connected pairs of terminating regions of its constituent MOSFET's, if the high voltage logic state occurs on input 11' and the low voltage logic state occurs on input 11. Then one or the other of MOSFET's 30 and 31, or both, are in the "on" condition, and for the small voltages which will occur across gate 18 in this circuit both of these MOSFET's will always be on in these circumstances. Reversing of the high and low voltage logic states on inputs 11 and 11' leads to transmission gate 18 being in the low conductivity condition between these common pairs of terminating regions. In this situation, MOSFET's 30 and 31 are always in the "off" condition. Thus, the circuit shown in FIG. 2B operates just in the manner described for the logic diagram system of FIG. 2A.
In the situation where MOSFET's 21 and 23 are in the "off" condition, the voltage at circuit node 15 is an inverted version of that of the logic state occurring at data latch data input 12 at the time that these transistors were switched into the "off" condition (assuming that the "hold time" and the "setup time" have each elapsed since the logic state change on terminal 12). This voltage is maintained by the feedback action of inverters 16 and 17 and transmission gate 18 in the feedback path arrangement as described above.
If, in this situation, the voltage at node 15 is that of the low voltage logic state, or "0" state, there will be a large voltage on the drain of "off" p-channel MOSFET 21 with respect to its substrate, the result being a substantial reverse bias voltage on the associated drain-substrate semiconductor pn junction. On the other hand, there will be relatively little reverse bias voltage across the drain-substrate junction of n-channel MOSFET 23 in the "off" condition.
If, alternatively, circuit node 15 is in the high voltage logic state, or "1" state, the reverse situation occurs. The drain-substrate semiconductor pn junction of "off" p-channel MOSFET 21 has relatively little reverse voltage bias. On the other hand, the drain-substrate junction of "off" n-channel MOSFET 23 has a relatively large reverse bias voltage thereon.
Similar statements are true at the common drain outputs of inverters 16 and 17. That is, since the electrically common drains of p-channel MOSFET 26 and n-channel MOSFET 27, together serving as an output for inverter 16, will always be in a logic state opposite that of circuit node 15, the drain-substrate semiconductor pn junction of transistor 26 will always have a large reverse bias thereon if the drain-substrate semiconductor pn junction of "off" p-channel MOSFET 21 has a relatively low reverse bias voltage on its corresponding junction. This is because circuit node 15 is in the high voltage level logic state thereby switching MOSFET 26 into the "off" condition. This statement concerning relative junction voltages is true, of course, only if any previous transient events occurring in the feedback path arrangement have fully propagated around this arrangement so that circuit node 15 voltages have reached stable values following the last preceding transient event.
On the other hand, there will be even less of a reverse bias voltage across the drain-substrate junction of n-channel MOSFET 27 than would occur in this circumstance across the drain-substrate junction of "off" p-channel MOSFET 21 because MOSFET 27 will be in the "on" condition. Of course, n-channel MOSFET 23 has a correspondingly large reverse bias voltage on its drain-substrate junction.
If circuit node 15, alternatively, is at a low voltage logic state, there will be a large reverse bias voltage across the drain-substrate semiconductor pn junction of MOSFET 27 which will be in the "off" condition. There will be a relatively small reverse bias voltage across the corresponding junction of "off" n-channel MOSFET 23. An even smaller reverse bias voltage will occur across the drain-substrate junction of p-channel MOSFET 26 because it will be switched into the "on" condition. There will, of course, be a correspondingly large reverse bias voltage across the drain-substrate junction of "off" p-channel MOSFET 21.
Further along the feedback path arrangement, the common drains of p-channel MOSFET 28 and n-channel MOSFET 29, serving as the output of inverter 17, will as previously described be in the same logic state as is circuit node 15. Thus, for a high voltage level logic state occurring on circuit node 15, there will be a relatively high reverse bias voltage across the drain-substrate junctions of both "off" n-channel MOSFET 23 and n-channel MOSFET 29 which will have been switched into the "off" condition also. There will be, however, an even smaller reverse bias voltage across the drain-substrate semiconductor pn junction of p-channel MOSFET 28 than there will be across the corresponding junction of "off" p-channel MOSFET 21 because MOSFET 28 will have been switched into the "on" condition.
The reverse of this situation will occur if circuit node 15 is in the low voltage level logic state. In this situation, p-channel MOSFET 28 will have been switched into the "off" condition and there will be a relatively large reverse bias voltage across the drain-substrate junction of MOSFET 28 and "off" p-channel MOSFET 21. There will correspondingly be a relatively low reverse bias voltage condition across the drain-substrate junctions of "off" n-channel MOSFET 23 and n-channel MOSFET 29, with the reverse bias voltage across MOSFET 29 being less than that of MOSFET 23 because MOSFET 29 will have been switched into the "on" condition.
As the foregoing description of drain-substrate semiconductor pn junctions demonstrates, there will always be at least one drain-substrate junction subjected to a substantial reverse bias voltage in the MOSFET devices used in inverters 16 and 17, and in controlled inverter 14, in situations where the enabling signals have switched MOSFET's 21 and 23 into the "off" condition to isolate the output of controlled inverter 14. In such situations, as previously explained, the logic state at circuit node 15 is that state which was present on latch input 12 at the switching of MOSFET's 21 and 23 into the "off" condition, and is maintained by the feedback path arrangement involving inverters 16 and 17 and transmission gate 18. This is a stable situation, and is one which will endure until the next switching of conditions of MOSFET's 21 and 23. At least this is true unless some transient event occurs leading to a decrease in such substantial reverse voltage bias of these semiconductor pn junctions which is of a sufficient duration to permit this transient result to propagate around the feedback path arrangement.
That is, if a substantially reverse biased drain-substrate junction suffers a significant reduction in the reverse bias voltage thereacross, and that reduction as a transient event propagates around the feedback path arrangement back to that junction to cause a further drop, the feedback path arrangement will reinforce this reduction to result in a change in logic state at circuit node 15. A source of such a transient event is the occurrence of a charge generating disturbance near such a reverse biased junction. Such disturbances are typically localized near the region where the disturbance is generated and is a temporary event; thus, such a disturbance is often termed a "single event upset."
A common source of such charge generating disturbances is particle radiation. Such particles impinging on a monolithic integrated circuit chip, will have "interactions" with the semiconductor material lattice structure and electrons along the paths thereof through the integrated circuit semiconductor material. This will result in raising the energy of the electrons involved into the conduction band and leaving corresponding holes in the valence band. Should such electron-hole pairs be generated sufficiently close to one of the reverse biased semiconductor pn junctions of the circuit of FIG. 2B, for instance, the electrons and holes so situated are subject to being collected by the action of electric fields in the region due to the reverse bias voltage thereacross and because of diffusion toward such a junction. The electrons and corresponding holes will be separated by the electric fields near the junction with the electrons attracted to the positive voltage side of the junction and the holes being attracted, or repelled, into the portions of the semiconductor material on the other side of the junction. This separation of electrons and holes, in effect, provides a temporary current flow from the positive voltage side of the semiconductor pn junction to the opposite side of this junction or, in effect, a radiation induced leakage current.
This current will be comprised of an immediate drift current component for electrons and holes which are immediately subject to such electric fields. A further component of this current will be provided by those electrons and holes which subsequently, by diffusion, move to be within the influence of such electric fields. Such current flows have the effect of discharging an n-type conductivity region placed at a positive voltage which gives it a reverse voltage bias with respect to a p-type conductivity region on the other side of the junction. Such a discharge current reduces this positive voltage. Conversely, such currents tend to charge a p-type conductivity region placed at a negative voltage to provide a reverse bias of that region with respect to a n-type conductivity region on the other side of the semiconductor pn junction. Such a charging acts to reduce the negative voltage to thereby reduce the reverse bias across that junction. Thus, in either situation, the charge generated by an impinging radiation particle would act in a manner to tend to reduce the magnitude of reverse bias voltages provided across substantially reverse biased semiconductor pn junctions separating p-type conductivity and n-type conductivity regions suffering such an impingement.
The effects of radiation particle impingement on regions of semiconductor material near a reverse biased semiconductor pn junction are a bit less severe for CMOS technology because either the n-channel MOSFET or the p-channel MOSFET in each pair will be formed in a "well" in the semiconductor material substrate, while the remaining member of the pair will be formed directly in the substrate. The devices provided directly in the substrate will have all of the risks for reverse biased semiconductor junctions therein due to radiation particle impingement thereabout as were described above. The other devices formed in "wells" in the semiconductor substrates will have some of the charge induced therein attracted or repelled by the fields at the semiconductor pn junction separating the well from the substrate and therefore will not all be affected by the electrical fields near the semiconductor pn junction separating the device drain region from the well.
Nevertheless, radiation particle impingement on a reverse biased drain region of either a n-channel or p-channel MOSFET, with the resulting reduction in the associated reverse bias voltage, poses a risk of a logic state change at circuit node 15 if this voltage reduction is propagated around the feedback path arrangement before the reverse bias voltage across the affected drain-substrate junction has sufficiently recovered its former value (assuming that the ENABLE signal is such that the feedback path has been established). This is a significant concern for use of the circuit of FIG. 2B in an environment in which significant particle radiation will occur.
A measure which has been used to reduce the rate of propagation of such a voltage reduction event about the feedback path arrangement has been the insertion of a resistance, 34, shown in dashed lines between the output of inverter 16 and the input of inverter 17 in FIGS. 2A and 2B. Resistance 34 is typically of a substantially high value which, combined with the parasitic capacitances at the gates of the MOSFET's in inverter 17, provides an increased time constant for transients in the feedback path arrangement. This results in an increase in the amount of time it takes for such a transient event to propagate around this feedback path arrangement.
However, the forming of a structure having a high value resistance for resistance 34 in CMOS technology in monolithic integrated circuits has a number of problems. As a result, often the only satisfactory way of forming a structure of a high resistance value in many fabrication processes is to form a polycrystalline silicon ("polysilicon") deposition which is relatively lightly doped with impurities to provide a high resistivity material which can then be formed into such a resistance.
However, such resistances are difficult to control in fabrication and so have a substantial variability in the resistance value achieved, and furthermore, have a substantial negative temperature coefficient of resistance. This means that the time constant about the feedback path arrangement decreases at higher temperatures because the resistance value of resistance 34 decreases. Such a result is undesirable because the current which can be supplied for a voltage recovery by circuit MOSFET's to a drain region which has suffered a radiation particle impingement with a resulting reverse bias voltage reduction cannot be as great at higher temperatures. This is because these MOSFET's controlling such current are able to only provide smaller currents at higher temperatures due to electron and hole mobilities decreasing at higher temperatures leading to greater "on" resistances in those MOSFET's in the "on" condition. This results in a lower effective channel conductance for a given gate voltage supplied for switching a MOSFET into, or keeping it in, the "on" condition.
Because the value of such resistance changes so greatly with temperature, the resistance value of resistance 34 also decreases substantially at lower temperatures, and may increase by an order of magnitude at lower temperatures. Such a result means a much larger time constant for signal propagations about the feedback path arrangement at these temperatures. This means there will be a considerable increase in the "setup" time which, as indicated above, is the time after a logic state has appeared at latch input 12 during which the enabling signals must not switch transistors 21 and 23 into the "off" condition to assure that the logic state occurring at latch input 12 has propagated around the feedback path arrangement to the output of inverter 17 so that this logic state will continue after the enabling signals isolate this feedback path arrangement from latch input 12. Such a result reduces the rate at which logic states can be changed and held in the D-type latch of FIGS. 2A and 2B which may reduce the rapidity of operations in a digital system using such a latch.
Thus, a D-type latch using a multiple inverter feedback arrangement would be desirable which is more resistant to single event upsets due to charge generating disturbances occurring in reverse bias drain-substrate semiconductor pn junctions. Further, such a latch should be able to perform in a similar manner in various portions of a substantial range of temperatures, and be conveniently provided in a monolithic integrated circuit.